Clock Synthesizer in 0.5pm CMOS
نویسنده
چکیده
This paper describes a 1.6GHz clock synthesizer which employs a delay locked loop (DLL) to generate multiple phases that are combined to produce the desired output clock frequency. A self correcting circuit ensures that the DLL arrives at the correct locked state irrespective of its power-up state or following either a wide variation in the input reference clock frequency or missing pulses in this clock signal. The measured edge peak-to-peak and rms jitter for a 1.6GHz output clock was 20ps and 3.lps respectively. The circuit is powered from a 3.3V supply and was fabricated on a 0.5pm generic digital CMOS process.
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